Verilog Code for Direct Linear Solver by Modified Gram Schimdt (MGS) Technique

A linear system y=Ax is solved here using square root free modified gram-Schimdt (SR_MGS) technique. Here, square root operation is bypassed and only division operation is required. The pseudo inverse computation is avoided. In this work, a prototype of the linear solver using SRF_MGS technique is given. This architecture is easily scalable to any parameter. The co-efficient matrix size is 8*4, the size of measurement matrix is of 4*1, and thus the size if x is also 4*1. The measurement matrix is stored in a ROM. The architecture uses maximum hardware sharing to have minimum resource consumption. Architecture uses 18-bit data width, and precision is of 10-bits. The simulation of this architecture is The track_x pulse is used to track the output estimation. The architecture is fully synchronous and designed with Verilog HDL with every block parameterized. The architecture is verified with VIVADO 2019 version and targeted to artix 7 fpga device.   [1]. S. Roy, D. P. Acharya, and A. K. Sahoo, “Fast omp algorithm and its fpga implementation for compressed sensing-based sparse signal acquisition systems,” IET Circuits, Devices & Systems, vol. n/a, no. n/a. [Online]. Available: https://ietresearch.onlinelibrary.wiley.com/doi/abs/10. 1049/cds2.12047 00 Share Share Whatsapp Post